Design metrics for gate oxide leakage characterization in nano-CMOS transistors

voltage, which represents the capacitive load of the transistor due to tunneling. This concisely encapsulates both qualitative as well as quantitative information about the swing in tunneling current during state transitions, while simultaneously accounting for the transition rate. We also investigate, via Monte Carlo simulations, the effect of process and design variations on the metrics. To the best of our knowledge, this is the first ever work that quantifies gate leakage during state transitions through the use of t eff C .